1. Field of the Invention
The present invention relates to a low-amplitude driver circuit and a semiconductor device including this, and more particularly relates to a low-amplitude driver circuit in which this output wiring and the output wiring of another driver circuit are adjacent, and a semiconductor device including this.
2. Description of the Related Art
Logic signals in a semiconductor chip generally have an amplitude with the ground potential (GND) as the minimum potential and the power supply potential (Vcc) as the maximum potential. In the case of signals with this kind of amplitude, if the later-stage circuit that receives these signals is a CMOS circuit (CMOS inverter, etc.), for example, then if the signal is at the ground potential (GND), P-channel MOS transistors in the CMOS circuit are turned on, and N-channel MOS transistors are turned off, and conversely, if the signal is at the power supply potential (Vcc), N-channel MOS transistors in the CMOS circuit are turned on, and P-channel MOS transistors are turned off.
However, if the later-stage circuit is not a CMOS circuit, but a circuit comprising transistors of one conduction type, such as N-channel MOS transistors for example, the logic signals supplied to this circuit need not necessarily have the kind of amplitude described above, and in this case it is sufficient to use the ground potential (GND) as the minimum potential and a potential lower than the power supply potential (Vcc-xcex1) as the maximum potential. That is to say, if the later-stage circuit does not include P-channel MOS transistors, it is not necessary to use a potential (in this case Vcc) that will turn the circuit completely off. Rather, by using a low amplitude in this way, not only is signal inversion made faster, making the circuit suitable for high-speed operation, but charging and discharging due to signal inversion is also reduced, resulting in lower power consumption. Thus, if the later-stage circuit is not CMOS, but a circuit comprising N-channel MOS transistors, a low amplitude is often used for the logic signals to be supplied to this circuit.
FIG. 15 is a drawing showing this kind of low-amplitude driver circuit. In the figure, three low-amplitude driver circuits, 400-0, 400-1, and 400-2, are shown. As these three low-amplitude driver circuits 400-0, 400-1, and 400-2 have the same circuit configuration, the actual circuit configuration is shown only for low-amplitude driver circuit 400-1 in the center, and the circuit configuration is not shown for the other low-amplitude driver circuits, 400-0 and 400-2.
These low-amplitude driver circuits 400-0, 400-1, and 400-2 receive and buffer input signals IN0, IN1, and IN2, respectively, and supply low-amplitude output signals to output signal lines X0, X1, and X2. As shown in the example of low-amplitude driver circuit 400-1, the actual circuit configuration comprises inverters 406 and 408, and N-channel MOS transistors 402 and 404. The N-channel MOS transistors 402 and 404 are connected in series between the power supply potential (Vcc) and the ground potential (GND), and the output of inverter 408 and the output of inverter 406, respectively, are applied to their gates. The input signal IN1 supplied to inverter 406 is a logic signal with an amplitude from the power supply potential (Vcc) to the ground potential (GND).
As shown in FIG. 15, the output signal lines X0, X1, and X2 are mutually parallel, and placed adjacent to each other, and there are coupling capacitances Cc between them.
Next, the operation of the low-amplitude driver circuits shown in FIG. 15 will be described, taking the example of the low-amplitude driver circuit 400-1. First, when the input signal IN1 is at the ground potential (GND), N-channel MOS transistor 402 is turned off and N-channel MOS transistor 404 is turned on, and therefore the output signal line X1 is connected to the ground potential (GND) and its potential is same as the ground potential (GND). Next, when the input signal IN1 changes to the power supply potential (Vcc), N-channel MOS transistor 402 is turned on and the N-channel MOS transistor 404 is turned off. As a result, the potential of the output signal line X1 rises, but as the turned-on transistor 402 is of N-channel type, the potential only rises to Vcc-Vtn (where Vtn is the threshold voltage of the N-channel MOS transistor 402).
In this way, the low-amplitude driver circuit 400-1 buffers the received input signal IN1, and supplies an output signal with an amplitude from GND to Vcc-Vtn to the output signal line X1. The other low-amplitude driver circuits, 400-0 and 400-2, operate in the same way.
A low-amplitude driver circuit of this kind is described in Japanese Patent Laid-Open No. 9-200036.
However, since output signal lines X0 and X2 are placed adjacent to and on either side of output signal line X1, as shown in FIG. 15, there are coupling capacitances Cc between these lines. Therefore, the potential of output signal line X1 is affected by changes in the potential of output signal lines X0 and X2.
FIG. 16 shows this situation, illustrating the case where output signal lines X0 and X2 adjacent to output signal line X1 change from the low level (GND) to the high level (Vcc-Vtn) while output signal line X1 is at the high level (Vcc-Vtn). As shown in FIG. 16, when output signal lines X0 and X2 change from the low level (GND) to the high level (Vcc-Vtn), output signal line X1 is raised by the coupling capacitances Cc. As described above, since transistor 402 is of N-channel type, when output signal line X1 rises at or above Vcc-Vtn, N-channel MOS transistor 402 goes to the off state, and the potential of output signal line X1 raised by the coupling capacitances Cc no longer falls.
When output signal line X1 rises at or above Vcc-Vtn, when input signal IN1 changes to the ground potential (GND) and N-channel MOS transistor 404 changes to the on state, it takes time to lower output signal line X1 to the ground potential (GND), preventing high-speed operation and also increasing power consumption.
Further, if output signal line X1 is raised by a large amount, and exceeds the power supply potential (Vcc), for example, an unexpected high voltage will be applied to the later-stage circuit connected to output signal line X1, causing reliability problems including degradation of transistor characteristics or permanent damage.
In particular, there has been a continuing reduction in the semiconductor chip wiring rule in recent years, and the affect of coupling capacitances Cc between the output signal lines has been increasing year by year.
The present invention therefore has as an object the provision of low-amplitude driver circuits wherein high-speed operation and low power consumption are secured, in particular, by preventing upward floating of output signal lines due to coupling capacitances Cc, and a semiconductor device that includes these.
A low-amplitude driver circuit according to the present invention is a low-amplitude driver circuit that is connected to a first and second power supply, and drives an output signal line in accordance with an input signal; comprising: first means for driving the above described output signal line to a prescribed potential between the potential of the above described first power supply and the potential of the above described second power supply when the above described input signal is at a first logic level, the above described first means being connected to said first power supply; second means for driving the above described output signal line to a the potential of the above described second power supply when the above described input signal is at a second logic level, the above described second means being connected to said second power supply; and third means for preventing fluctuation of the potential of the above described output signal line toward the potential of the above described first power supply as seen from the above described prescribed potential.